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AMD May Adopt New Chip Stacking Technology for Compact Stacking and Interconnect, with Partial Chip Overlap

kyojuro Sunday, November 24, 2024

AMD recently unveiled the Ryzen 7 9800X3D, a cutting-edge gaming processor that incorporates 3D Vertical Cache (3D V-Cache) technology on the Zen 5 architecture. Boasting 8 cores and 16 threads, this processor enhances the L3 cache from 32MB in its standard model to an impressive 96MB, resulting in a total cache capacity of 104MB. Its outstanding gaming capabilities have propelled the Ryzen 7 9800X3D to popularity within the DIY market, where it even commands a premium on second-hand trading platforms.

Ryzen 7 9800X3D

Wccftech reports that AMD has filed a patent for an innovative "multi-chip stacking" process in upcoming Ryzen SoCs. This novel packaging design facilitates compact chip stacking and interconnections via overlapping chip sections. By layering smaller chips with larger sections, AMD aims to allocate room for additional components and functionalities within the same chip.

This methodology intends to optimize contact efficiency, maximizing core counts, cache sizes, and memory bandwidth all within unchanged chip dimensions. By overlapping smaller chips, the design minimizes interconnect latency, fostering rapid communication among chip sections. Additionally, enhanced power management is achievable, as power gating allows for superior control over each unit through separated smaller chips.

Multi-Chip Stacking

The X3D processor line, which pioneered 3D V-Cache technology, has made waves in the consumer market. Coupled with dominant data center products, surpassing Intel, this new stacking strategy is poised to influence AMD's future EPYC and Ryzen offerings. Over recent years, AMD has shifted from single-chip designs toward 3D chiplet architecture. Owing to the complexity of this design, a considerable period may be required to transition from patenting to production and release.

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